Often decoupling capacitors are added to a printed circuit board and connected to certain power or voltage supply leads, and/or certain critical signal leads on a semiconductor chip having integrated circuits therein to reduce switching noise, to reduce the amount of electromagnetic energy radiated from the semiconductor chip, and/or to reduce or prevent excessive voltage ripples. Also, bulk capacitors (typically larger than the decoupling capacitors) are sometimes used as well, but may not be critical and may not be needed. In such cases where bulk capacitors are also used, the bulk capacitors may be used to filter low-frequency voltage ripple and/or to more quickly recharge the decoupling capacitors.
Decoupling capacitors are also sometimes referred to as bypass capacitors in the art. Furthermore, the term “lead” is used generically herein to refer to any type of electrical connector on a packaged semiconductor chip for electrically connecting the packaged chip to another packaged chip or to a circuit board, including (but not necessarily limited to): solder bumps or solder balls on a ball grid array package, pins on a pin grid array package, or leads on a TSOP package, for example. As will be apparent to one of ordinary skill in the art, “leads” of a chip, as well as chip configurations, vary widely and will likely continue to evolve and change in the future.
A specification of a decoupling capacitor that may be considered while selecting a decoupling capacitor is its self-resonant frequency. Generally, a capacitor remains capacitive up to its self-resonance frequency. Above the self-resonance frequency, the capacitor may start to appear as an inductor. FIG. 1 illustrates a series equivalent circuit 20 of a capacitor. Generally, each capacitor has three different components: equivalent series resistance (ESR), equivalent series inductance (ESL), and the capacitance itself (C). The self-resonant frequency typically occurs at the point where the impedance of the capacitor (C) is equal to the impedance of the inductor (ESL). This relationship is illustrated by the following equations.
      Z    C    =      1          ω      ⁢                          ⁢      C      
where ZC is impedance for the capacitor (C in FIG. 1), ω is frequency in radians (ω=2πf), and C is capacitance of the capacitor (C in FIG. 1).ZL=ωL,
where ZL is impedance for the inductor (ESL in FIG. 1) and L is inductance of the inductor (ESL in FIG. 1). At resonant frequency:
                    Z        C            =              Z        L              ,                  1                  ω          ⁢                                          ⁢          C                    =              ω        ⁢                                  ⁢        L              ⁢        
            ω      2        =                            1                      L            ⁢                                                  ⁢            C                          ⁢                                  ⁢        and        ⁢                                  ⁢        ω            =              2        ⁢                                  ⁢        π        ⁢                                  ⁢        f              ,where f is frequency,
            f      R        =          1              2        ⁢                                  ⁢        π        ⁢                              L            ⁢                                                  ⁢            C                                ,where fR is the self-resonance frequency.
As shown in the self-resonance equation (fR) above, a lower capacitance and a lower inductance yield a higher resonant frequency. A goal of using decoupling capacitors is to provide a low impedance path from a power supply to ground to shunt unwanted radio frequency (RF) energy, for example. Thus, it is typically desirable to choose a low inductance capacitor for a decoupling capacitor.
In a prior method, decoupling capacitors and bulk capacitors are distributed uniformly around the chip. Many of today's chips are complex and have systems on the chip (e.g., system-on-chip layout). Such chips typically have multiple types of devices, such as a analog PLL (phase locked loop) component, digital PLL component, general purpose processor, digital signal processor, ROM memory, RAM memory, digital bandgap, analog bandgap, voltage regulator, memory interface, clock circuitry, and combinations thereof, for example. In such chips having several different devices therein, such devices may be operating at different switching speeds (i.e., different clock frequencies), different voltages, and/or different currents. Generally, a higher switching frequency requires a smaller decoupling capacitor to sufficiently reduce the noise level, and a lower switching frequency requires a larger decoupling capacitor to sufficiently reduce the noise level. In such complex chips having two or more switching frequencies from multiple devices on the chip, a uniform distribution of same size decoupling capacitors may yield a non-uniform noise level across the chip. If the noise level is not uniform across the chip, it may create an antenna effect, which may result in more electromagnetic energy radiating from the chip during operation. This is commonly referred to as a differential mode radiation.
FIG. 2 is a bottom view of a simplified schematic for an example packaged chip 30 with uniformly distributed decoupling capacitors 32 and bulk capacitors 34, as is common in the prior art. FIG. 3 is a side view of the packaged chip 30 and the capacitors 32, 34 of FIG. 2 operably mounted on a circuit board 36, for example. FIG. 4 shows a simplified electrical schematic 40 of how a decoupling capacitor and a bulk capacitor are typically connected to a chip lead for filtering unwanted noise.
Referring to FIG. 2, note that all of the decoupling capacitors 32 have the same values (0.01 μF), and note that all of the bulk capacitors 34 have the same values (22 μF). Also, note that the number of decoupling capacitors 32 and placement is the same on each side of the chip 30. However, the chip 30 shown in FIG. 2 is a system-on-chip device having a digital portion 42 (e.g., digital PLL, digital signal processor, general purpose processor), an analog portion 44 (e.g., analog PLL), and memory interfaces (e.g., external memory interface fast or EMIFF), for example. Each of these components of the chip 30 may operate at different switching speeds (different clock frequencies), different voltages, and/or different peak switching currents. Thus, with the uniform distribution of decoupling capacitors 32 shown in FIG. 2, the overall noise level across the chip 30 may not be uniform. This may cause a significant noise differential across the chip 30 and may lead to differential mode radiation, which is usually not desirable.
Typically chips and boards used or sold in the U.S. must pass FCC certification for the level of electromagnetic energy radiated from the device during operation (e.g., transmission of radio frequency signals generated by high frequency components on a chip generating noise leading to differential mode radiation). Generally, the larger the size of the chip, the greater the antenna effect generated by non-uniform noise levels across the chip. And, most complex chips today are growing in size and number of leads as more devices and systems are placed on the chip to increase system speeds and decrease power consumption, for example. Thus, if a chip has some level of noise, it is preferred to have the noise level as uniform as possible across or around the chip to reduce or eliminate the antenna effect. Hence, a need exists for a way to provide a more uniform noise level across a chip, especially as chip sizes increase, as the number of leads increases, and as multiple components running at different clock frequencies are placed on a single chip, for example.